Publications:
GitHub:
Journal Publications
j18. Vedika Saravanan and Samah Mohamed Saeed, “Noise Adaptive Quantum Circuit Mapping Using Reinforcement Learning and Graph Neural Network,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2023.3340608.
j17. Vedika Saravanan and Samah Mohamed Saeed, “Data-Driven Reliability Models of Quantum Circuit: From Traditional ML to Graph Neural Network,” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022, doi: 10.1109/TCAD.2022.3202430.
j16. 1. Ammar Kirmani, Kieran Bull, Chang-Yu Hou, Vedika Saravanan, Samah Mohamed Saeed, Zlatko Papić, Armin Rahmani, and Pouyan Ghaemi, “Probing Geometric Excitations of Fractional Quantum Hall States on Quantum Computers,” Phys. Rev. Lett., vol. 129, no. 5, p. 056801, Jul. 2022, doi: 10.1103/PhysRevLett.129.056801.
j15. Vedika Saravanan and Samah Mohamed Saeed, “Pauli Error Propagation-Based Gate Rescheduling for Quantum Circuit Error Mitigation,” in IEEE Transactions on Quantum Engineering, vol. 3, pp. 1-11, 2022, Art no. 2500111, doi: 10.1109/TQE.2022.3161197.
j14. Nikita Acharya, Miroslav Urbanek, Wibe A. de Jong, Samah Mohamed Saeed, “Test Points for Online Monitoring of Quantum Circuits,” ACM Journal on Emerging Technologies in Computing (JETC), 2021.
j13. Janusz Kusyk, Samah Mohamed Saeed and Muharrem Umit Uyar, “Survey on Quantum Circuit Compilation for Noisy Intermediate-Scale Quantum Computers: Artificial Intelligence to Heuristics,” IEEE Transactions on Quantum Engineering, vol. 2, pp. 1-16, 2021, Art no. 2501616, doi: 10.1109/TQE.2021.3068355.
j12. Kanad Basu, Samah Mohamed Saeed, Pilato Christian, Mohammad Ashraf, Mohammad Thari Nabeel, Krishnendu Chakrabarty, and Ramesh Karri, “CAD-Base: An Attack Vector into the Electronics Supply Chain,” ACM Transactions on Design Automation of Electronic Systems (TODAES). vol. 24, no. 38, pp.4, 2019.
j11. Samah Mohamed Saeed, Robert Wille, and Ramesh Karri, “Locking the Design of Building Blocks for Quantum Circuits,” ACM Trans. Embed. Comput. Syst., vol. 18, no. 5s, pp. 60:1–60:15, Oct. 2019.
j10. Samah Mohamed Saeed, Alwin Zulehner, Robert Wille, Rolf Drechsler, Ramesh Karri, “Reversible Circuits: IC/IP Piracy Attacks and Countermeasures,” in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 11, pp. 2523-2535, Nov. 2019.
j9. Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Ramesh Karri, and Robert Will, “Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits,” ACM Journal on Emerging Technologies in Computing (JETC), vol. 15, no. 3, pp. 23:1-23:17, 2019.
j8. Xiaotong Cui, Samah Mohamed Saeed, Alwin Zulehner. Robert Wille, Kaijie Wu, Rolf Drechsler, Ramesh Karri, “On the Difficulty of Inserting Trojans in Reversible Computing Architectures,” IEEE Transactions on Emerging Topics in Computing, 2018. [Online]. Available: http://doi: 10.1109/TETC.2018.2823315.
j7. Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, “Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers,” IEEE Transactions on Emerging Topics in Computing, vol. 5, no. 3, pp. 317-328, 2017.
j6. Samah Mohamed Saeed and Ozgur Sinanoglu, “A comprehensive Design-for-Test Infrastructure in the Context of Security- Critical Applications,” IEEE Design & Test, vol. 34, no. 1, pp. 57-64, Feb. 2017.
j5. Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, and Ramesh Karri, “Novel Test- Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures,” Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, issue 5, pp. 808-821, May. 2015.
j4. Samah Mohamed Saeed and Ozgur Sinanoglu, “DfT Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing,” IEEE Transactions on Very Large Scale Integration Systems, vol. 22, issue 3, pp. 516-521, Mar. 2014.
j3. Samah Mohamed Saeed, Ozgur Sinanoglu, and Sobeeh Almukhaizim, “Predictive Techniques for Projecting Test Data Compression,” IEEE Transactions on Very Large Scale Integration Systems, vol.21, no.9, pp. 1762-1766, Sep. 2013.
j2. Samah Mohamed Saeed and Ozgur Sinanoglu, “Expedited-Compact Architecture for Average Scan Power Reduction,” IEEE Design and Test of Computers, vol.30, no.3, pp.25- 33, Jun. 2013.
j1. Samah Mohamed Saeed and Ozgur Sinanoglu, “Multi-Modal Response Compaction Adaptive to X-Density Variation,” IET Computer and Digital Techniques, vol. 2, issue 6, pp. 69-77, Mar. 2012.
Conference Publications
c24. Christian Rasmussen and Samah Mohamed Saeed, “Time-Aware Re-synthesis for Secure Quantum Systems,” 2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), Tysons Corner, VA, USA, 2024, pp. 01-06, doi: 10.1109/HOST55342.2024.10545389.
c23. Vedika Saravanan, Mohammad Walid Charrwi, and Samah Mohamed Saeed, “Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation,” in proceedings the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 339-344, 2023.
c22. Vedika Saravanan and Samah Mohamed Saeed, “Graph Neural Networks for Idling Error Mitigation,” IEEE/ACM International Conference On Computer Aided Design (ICCAD), 2022. (Acceptance rate: 22%)
c21. Vedika Saravanan and Samah Mohamed Saeed, “Machine Learning for Quantum Hardware Performance Assessment,” accepted at IEEE International Conference on Computer Design (ICCD), 2022.
c20. Mohammad Walid Charrwi, Huy Phan, Bo Yuan, and Samah Mohamed Saeed, “Towards Yield Improvement for AI Accelerators: Analysis and Exploration,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2022.
c19. Nikita Acharya and Samah Mohamed Saeed, “Automated Flag Qubit Insertion for Reliable Quantum Circuit Output,” IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2021, pp. 431-436, doi: 10.1109/ISVLSI51109.2021.00085.
c18. Vedika Saravanan and Samah Mohamed Saeed, “Test Data-Driven Machine Learning Models for Reliable Quantum Circuit Output,” IEEE European Test Symposium (ETS), 2021, pp. 1-6.
c17. Vedika Saravanan and Samah Mohamed Saeed, “Decomposition-Based Watermarking of Quantum Circuits,” International Symposium on Quality Electronic Design (ISQED), 2021, pp. 73-78.
c16. Nikita Acharya, and Samah Mohamed Saeed, “A Lightweight Approach to Detect Malicious/Unexpected Changes in the Error Rates of NISQ Computers,” IEEE/ACM International Conference On Computer Aided Design (ICCAD), San Diego, CA, USA, 2020, pp. 1-9. (Acceptance rate %20-%24)
c15. Reginald Tetteh, Samah Mohamed Saeed, “Analysis of Test Data Tampering Attack on Manufacturing Testing,” 2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2020, pp. 1-6, doi: 10.1109/DTIS48698.2020.9081029.
c14. Samah Mohamed Saeed, Xiaotong Cui, Alwin Zulehner, Robert Wille, Kaijie Wu, Rolf Drechsler and Ramesh Karri, “IP Piracy Assessment of Reversible Logic,” IEEE/ACM International Conference On Computer Aided Design, pp. 1-8, 2018. (Acceptance rate %20-%24)
c13. Samah Mohamed Saeed, Nithin Mahendran, Alwin Zulehner, Ramesh Karri, and Robert Wille, “Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks,” IEEE/ACM International Conference on Computer Design, USA, pp. 537–540, 2017.
c12. Bodhisatwa Mazumdar, Samah Mohamed Saeed, Sk Subidh Ali, and Ozgur Sinanoglu, “Thwarting Timing Attacks on NEMS Relay Based Designs,” IEEE VLSI Test Symposium, USA, pp. 1-4, 2016.
c11. Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan Rajendran, and Ozgur Sinanoglu,“Activation of Logic Encrypted Chips: Pre-Test or Post-Test?,” IEEE Design, Automation, And Test In Europe, Germany, pp. 139-144, 2016.
c10. Samah Mohamed Saeed, Bodhisatwa Mazumdar, Sk Subidh Ali, Ozgur Sinanoglu, “Timing Attack on NEMS Relay Based Design of AES,” IFIP/IEEE International Conference on Very Large Scale Integration, USA, pp. 264-269, 2015.
c9. Samah Mohamed Saeed and Ozgur Sinanoglu, “DfST: Design for Secure Testability,”IEEE International Test Conference, USA, pp. 1-10, 2014.
c8. Samah Mohamed Saeed, Sk Subidh Ali, Ozgur Sinanoglu, and Ramesh Karri, “Novel Test- Mode-Only Scan Attack for Contemporary Scan Architectures,” IEEE International Test Conference, USA, pp. 1-8, 2014. (Acceptance rate %22)
c7. Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, and Ramesh Karri, “New Scan Attacks Against State-of-the-art Countermeasures and DFT,” IEEE International Symposium on Hardware-Oriented Security and Trust, Arlington, USA, pp. 142-147, 2014.
c6. Abishek Ramdas, Samah Mohamed Saeed, and Ozgur Sinanoglu, “Slack Removal for Enhanced Reliability and Trust,” IEEE Design & Technology of Integrated Systems in Nanoscale Era, Santorini, Greece, pp. 1-4, 2014.
c5. Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, and Ramesh Karri, “New Scan- Based Attack Using Only the Test Mode,” IEEE International Conference on Very Large Scale Integration, Istanbul, Turkey, pp. 234-239, 2013.
c4. Sk Subidh Ali, Samah Mohamed Saeed, Ozgur Sinanoglu, and Ramesh Karri, “Scan Attack in the Presence of Mode-Reset Countermeasure,” IEEE International On-Line Testing Symposium, Crete, Greece, pp. 230-231, 2013.
c3. Samah Mohamed Saeed and Ozgur Sinanoglu, “DfT Support for Launch and Capture Power Reduction in Launch-Off-Capture Testing,” IEEE European Test Symposium, Annecy, France, pp. 1-6, 2012.
c2. Samah Mohamed Saeed and Ozgur Sinanoglu, “Expedited Response Compaction for Scan Power Reduction,” IEEE VLSI Test Symposium, Dana Point, CA, USA, pp. 40-45, 2011. (Best paper award)
c1. Samah Mohamed Saeed and Ozgur Sinanoglu, “XOR-Based Response Compactor Adaptive to X-Density Variation,” IEEE Asian Test Symposium, Shanghai, China, pp. 212- 217, 2010.